URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] - Rev 18

Rev	Log message	Author	Age	Path
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5228d 08h	/pit/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5242d 05h	/pit/
16	Added master error counter variable, added simulation timout limit	rehayes	5353d 08h	/pit/
15	Fix blocking assigment	rehayes	5381d 08h	/pit/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5450d 06h	/pit/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5480d 10h	/pit/
12	Fixed for single cycle reads	rehayes	5481d 05h	/pit/
11	Changed read task to capture data at rising edge of clock	rehayes	5481d 05h	/pit/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5482d 08h	/pit/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5488d 01h	/pit/
8	Fix ack signal in testbench	rehayes	5488d 02h	/pit/
7	Reflection of minor corrections	rehayes	5492d 08h	/pit/
6	Reflection of minor corrections	rehayes	5492d 08h	/pit/
5		rehayes	5530d 04h	/pit/
4	Initial Release March 14, 2009 - Bob Hayes	rehayes	5530d 04h	/pit/
3	Initial Release March 14, 2009 - Bob Hayes	rehayes	5530d 05h	/pit/
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5530d 05h	/pit/
1	The project was created and the structure was created	root	5530d 20h	/pit/