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Rev Log message Author Age Path
19 Minor change to add parameter to pit instance rehayes 5221d 13h /pit/
18 Traded 16 data registers for 3 address registers when wait states are enabled. rehayes 5221d 16h /pit/
17 Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle. rehayes 5235d 12h /pit/
16 Added master error counter variable, added simulation timout limit rehayes 5346d 15h /pit/
15 Fix blocking assigment rehayes 5374d 16h /pit/
14 Cosmetic update, changed no-blocking assigment to blocking assigment rehayes 5443d 13h /pit/
13 Update to rev 0.3, added SINGLE_CYCLE parameter rehayes 5473d 17h /pit/
12 Fixed for single cycle reads rehayes 5474d 12h /pit/
11 Changed read task to capture data at rising edge of clock rehayes 5474d 12h /pit/
10 Added SINGLE_CYCLE parameter for WISHBONE bus cycles rehayes 5475d 15h /pit/
9 fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice. rehayes 5481d 09h /pit/
8 Fix ack signal in testbench rehayes 5481d 09h /pit/
7 Reflection of minor corrections rehayes 5485d 15h /pit/
6 Reflection of minor corrections rehayes 5485d 15h /pit/
5 rehayes 5523d 11h /pit/
4 Initial Release March 14, 2009 - Bob Hayes rehayes 5523d 11h /pit/
3 Initial Release March 14, 2009 - Bob Hayes rehayes 5523d 12h /pit/
2 Initial Release March 14, 2009 - Bob Hayes rehayes 5523d 12h /pit/
1 The project was created and the structure was created root 5524d 03h /pit/

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