URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] - Rev 23

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
23	Simple language upgrade, will make bigger changes to add more system verilog features later.	rehayes	4691d 03h	/pit/
22	Correct revision, compiles with VCS.	rehayes	4691d 03h	/pit/
21	Simple language upgrade	rehayes	4691d 19h	/pit/
20	minor update for timing constraint sugestions.	rehayes	5226d 21h	/pit/
19	Minor change to add parameter to pit instance	rehayes	5226d 22h	/pit/
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5227d 00h	/pit/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5240d 21h	/pit/
16	Added master error counter variable, added simulation timout limit	rehayes	5351d 23h	/pit/
15	Fix blocking assigment	rehayes	5380d 00h	/pit/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5448d 22h	/pit/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5479d 02h	/pit/
12	Fixed for single cycle reads	rehayes	5479d 21h	/pit/
11	Changed read task to capture data at rising edge of clock	rehayes	5479d 21h	/pit/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5481d 00h	/pit/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5486d 17h	/pit/
8	Fix ack signal in testbench	rehayes	5486d 18h	/pit/
7	Reflection of minor corrections	rehayes	5490d 23h	/pit/
6	Reflection of minor corrections	rehayes	5490d 23h	/pit/
5		rehayes	5528d 19h	/pit/
4	Initial Release March 14, 2009 - Bob Hayes	rehayes	5528d 20h	/pit/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pit

[/] [pit/] - Rev 23

Filtering Options