URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] - Rev 23

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
23	Simple language upgrade, will make bigger changes to add more system verilog features later.	rehayes	4741d 11h	/pit/
22	Correct revision, compiles with VCS.	rehayes	4741d 11h	/pit/
21	Simple language upgrade	rehayes	4742d 03h	/pit/
20	minor update for timing constraint sugestions.	rehayes	5277d 05h	/pit/
19	Minor change to add parameter to pit instance	rehayes	5277d 05h	/pit/
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5277d 08h	/pit/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5291d 04h	/pit/
16	Added master error counter variable, added simulation timout limit	rehayes	5402d 07h	/pit/
15	Fix blocking assigment	rehayes	5430d 08h	/pit/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5499d 06h	/pit/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5529d 09h	/pit/
12	Fixed for single cycle reads	rehayes	5530d 05h	/pit/
11	Changed read task to capture data at rising edge of clock	rehayes	5530d 05h	/pit/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5531d 08h	/pit/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5537d 01h	/pit/
8	Fix ack signal in testbench	rehayes	5537d 02h	/pit/
7	Reflection of minor corrections	rehayes	5541d 07h	/pit/
6	Reflection of minor corrections	rehayes	5541d 07h	/pit/
5		rehayes	5579d 03h	/pit/
4	Initial Release March 14, 2009 - Bob Hayes	rehayes	5579d 04h	/pit/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pit

[/] [pit/] - Rev 23

Filtering Options