URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] [trunk/] - Rev 18

Rev	Log message	Author	Age	Path
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5377d 06h	/pit/trunk/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5391d 03h	/pit/trunk/
16	Added master error counter variable, added simulation timout limit	rehayes	5502d 05h	/pit/trunk/
15	Fix blocking assigment	rehayes	5530d 06h	/pit/trunk/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5599d 04h	/pit/trunk/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5629d 07h	/pit/trunk/
12	Fixed for single cycle reads	rehayes	5630d 03h	/pit/trunk/
11	Changed read task to capture data at rising edge of clock	rehayes	5630d 03h	/pit/trunk/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5631d 06h	/pit/trunk/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5636d 23h	/pit/trunk/
8	Fix ack signal in testbench	rehayes	5637d 00h	/pit/trunk/
7	Reflection of minor corrections	rehayes	5641d 05h	/pit/trunk/
6	Reflection of minor corrections	rehayes	5641d 05h	/pit/trunk/
5		rehayes	5679d 01h	/pit/trunk/
4	Initial Release March 14, 2009 - Bob Hayes	rehayes	5679d 02h	/pit/trunk/
3	Initial Release March 14, 2009 - Bob Hayes	rehayes	5679d 02h	/pit/trunk/
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5679d 02h	/pit/trunk/
1	The project was created and the structure was created	root	5679d 17h	/pit/trunk/