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[/] [pit/] [trunk/] - Rev 19

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Rev Log message Author Age Path
19 Minor change to add parameter to pit instance rehayes 5227d 18h /pit/trunk/
18 Traded 16 data registers for 3 address registers when wait states are enabled. rehayes 5227d 21h /pit/trunk/
17 Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle. rehayes 5241d 17h /pit/trunk/
16 Added master error counter variable, added simulation timout limit rehayes 5352d 20h /pit/trunk/
15 Fix blocking assigment rehayes 5380d 21h /pit/trunk/
14 Cosmetic update, changed no-blocking assigment to blocking assigment rehayes 5449d 18h /pit/trunk/
13 Update to rev 0.3, added SINGLE_CYCLE parameter rehayes 5479d 22h /pit/trunk/
12 Fixed for single cycle reads rehayes 5480d 17h /pit/trunk/
11 Changed read task to capture data at rising edge of clock rehayes 5480d 17h /pit/trunk/
10 Added SINGLE_CYCLE parameter for WISHBONE bus cycles rehayes 5481d 20h /pit/trunk/
9 fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice. rehayes 5487d 14h /pit/trunk/
8 Fix ack signal in testbench rehayes 5487d 14h /pit/trunk/
7 Reflection of minor corrections rehayes 5491d 20h /pit/trunk/
6 Reflection of minor corrections rehayes 5491d 20h /pit/trunk/
5 rehayes 5529d 16h /pit/trunk/
4 Initial Release March 14, 2009 - Bob Hayes rehayes 5529d 16h /pit/trunk/
3 Initial Release March 14, 2009 - Bob Hayes rehayes 5529d 17h /pit/trunk/
2 Initial Release March 14, 2009 - Bob Hayes rehayes 5529d 17h /pit/trunk/
1 The project was created and the structure was created root 5530d 08h /pit/trunk/

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