URL https://opencores.org/ocsvn/pit/pit/trunk

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[/] [pit/] [trunk/] [rtl/] - Rev 24

Rev	Log message	Author	Age	Path
24	Added System Verilog Wishbone interface to module and testbench.	rehayes	4655d 16h	/pit/trunk/rtl/
22	Correct revision, compiles with VCS.	rehayes	4741d 03h	/pit/trunk/rtl/
21	Simple language upgrade	rehayes	4741d 20h	/pit/trunk/rtl/
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5277d 01h	/pit/trunk/rtl/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5290d 21h	/pit/trunk/rtl/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5498d 22h	/pit/trunk/rtl/
12	Fixed for single cycle reads	rehayes	5529d 21h	/pit/trunk/rtl/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5531d 00h	/pit/trunk/rtl/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5536d 18h	/pit/trunk/rtl/
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5578d 21h	/pit/trunk/rtl/