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[/] [pit/] [trunk/] [rtl/] - Rev 17

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Rev Log message Author Age Path
17 Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle. rehayes 5391d 03h /pit/trunk/rtl/
14 Cosmetic update, changed no-blocking assigment to blocking assigment rehayes 5599d 04h /pit/trunk/rtl/
12 Fixed for single cycle reads rehayes 5630d 03h /pit/trunk/rtl/
10 Added SINGLE_CYCLE parameter for WISHBONE bus cycles rehayes 5631d 06h /pit/trunk/rtl/
9 fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice. rehayes 5636d 23h /pit/trunk/rtl/
2 Initial Release March 14, 2009 - Bob Hayes rehayes 5679d 03h /pit/trunk/rtl/

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