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[/] [pit/] [trunk/] [rtl/] - Rev 18

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Rev Log message Author Age Path
18 Traded 16 data registers for 3 address registers when wait states are enabled. rehayes 5239d 06h /pit/trunk/rtl/
17 Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle. rehayes 5253d 02h /pit/trunk/rtl/
14 Cosmetic update, changed no-blocking assigment to blocking assigment rehayes 5461d 03h /pit/trunk/rtl/
12 Fixed for single cycle reads rehayes 5492d 02h /pit/trunk/rtl/
10 Added SINGLE_CYCLE parameter for WISHBONE bus cycles rehayes 5493d 05h /pit/trunk/rtl/
9 fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice. rehayes 5498d 23h /pit/trunk/rtl/
2 Initial Release March 14, 2009 - Bob Hayes rehayes 5541d 02h /pit/trunk/rtl/

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