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[/] [pit/] [trunk/] [rtl/] [verilog/] - Rev 17

Rev	Log message	Author	Age	Path
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5260d 15h	/pit/trunk/rtl/verilog/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5468d 17h	/pit/trunk/rtl/verilog/
12	Fixed for single cycle reads	rehayes	5499d 15h	/pit/trunk/rtl/verilog/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5500d 19h	/pit/trunk/rtl/verilog/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5506d 12h	/pit/trunk/rtl/verilog/
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5548d 15h	/pit/trunk/rtl/verilog/