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[/] [pit/] [trunk/] [rtl/] [verilog/] - Rev 23

Rev	Log message	Author	Age	Path
21	Simple language upgrade	rehayes	4707d 22h	/pit/trunk/rtl/verilog/
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5243d 02h	/pit/trunk/rtl/verilog/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5256d 23h	/pit/trunk/rtl/verilog/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5465d 00h	/pit/trunk/rtl/verilog/
12	Fixed for single cycle reads	rehayes	5495d 23h	/pit/trunk/rtl/verilog/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5497d 02h	/pit/trunk/rtl/verilog/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5502d 19h	/pit/trunk/rtl/verilog/
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5544d 23h	/pit/trunk/rtl/verilog/