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352 linus 5533d 21h /plasma/tags/V2_1/vhdl/
350 root 5562d 16h /plasma/tags/V2_1/vhdl/
127 This commit was manufactured by cvs2svn to create tag 'V2_1'. 7299d 04h /plasma/tags/V2_1/vhdl/
125 Fixed pc_source_type comment. rhoads 7299d 04h /plasma/tags/V2_1/vhdl/
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7299d 04h /plasma/tags/V2_1/vhdl/
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7366d 04h /plasma/tags/V2_1/vhdl/
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7430d 05h /plasma/tags/V2_1/vhdl/
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7441d 17h /plasma/tags/V2_1/vhdl/
120 Make generics "GENERIC" rhoads 7441d 17h /plasma/tags/V2_1/vhdl/
119 Opcodes from count.c rhoads 7480d 04h /plasma/tags/V2_1/vhdl/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7480d 04h /plasma/tags/V2_1/vhdl/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7480d 04h /plasma/tags/V2_1/vhdl/
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7480d 04h /plasma/tags/V2_1/vhdl/
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7480d 04h /plasma/tags/V2_1/vhdl/
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7480d 04h /plasma/tags/V2_1/vhdl/
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.
rhoads 7480d 04h /plasma/tags/V2_1/vhdl/
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7480d 04h /plasma/tags/V2_1/vhdl/
108 changed interrupt vector from 0x30 to 0x3c rhoads 7754d 01h /plasma/tags/V2_1/vhdl/
107 merged rising_edge(clk) statements rhoads 7754d 01h /plasma/tags/V2_1/vhdl/
106 better test mem_pause rhoads 7757d 03h /plasma/tags/V2_1/vhdl/

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