URL https://opencores.org/ocsvn/plasma/plasma/trunk

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[/] [plasma/] [tags/] [V3_0/] - Rev 19

Rev	Log message	Author	Age	Path
19	Changed simili run to 40us.	rhoads	8216d 17h	/plasma/tags/V3_0/
18	Fixed "divu $3,$4". "Div $3,$4" still has bug if $3*$4<0.	rhoads	8216d 17h	/plasma/tags/V3_0/
17	Fixed "blez $0,target". Made LWL=LW and SWL=SW. Changed tabs to spaces.	rhoads	8216d 17h	/plasma/tags/V3_0/
16	Fixed binary to HEX when the number of digits isn't a multiple of 4.	rhoads	8216d 17h	/plasma/tags/V3_0/
15	Test all MIPS I opcodes.	rhoads	8216d 17h	/plasma/tags/V3_0/
14	Fixed big-endian mode bugs	rhoads	8220d 16h	/plasma/tags/V3_0/
13	Removed reg_bank configuration control	rhoads	8220d 16h	/plasma/tags/V3_0/
12	Better support for dual-port memories, removed old method	rhoads	8220d 16h	/plasma/tags/V3_0/
11	Added comment for DEBUG mode	rhoads	8220d 16h	/plasma/tags/V3_0/
10	Add pause_in to process dependency, fixes "lw $4,0($4)"	rhoads	8220d 16h	/plasma/tags/V3_0/
9	Support for generic_tpram dual-port RAM	rhoads	8225d 20h	/plasma/tags/V3_0/
8	Preparing to use dual-port memory for registers.	rhoads	8226d 17h	/plasma/tags/V3_0/
7	Made writes 4 cycles, improved mem_ctrl.vhd	rhoads	8232d 00h	/plasma/tags/V3_0/
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8235d 22h	/plasma/tags/V3_0/
4	Update web page	rhoads	8454d 22h	/plasma/tags/V3_0/
2	MIPS-lite CPU core	rhoads	8454d 23h	/plasma/tags/V3_0/
1	Standard project directories initialized by cvs2svn.		8454d 23h	/plasma/tags/V3_0/