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[/] [plasma/] [tags/] [V3_0/] [vhdl/] - Rev 115

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Rev	Log message	Author	Age	Path
115	Matthias Grunewald's changes for Xilinx FPGA dual-port RAM.	rhoads	7508d 08h	/plasma/tags/V3_0/vhdl/
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7508d 08h	/plasma/tags/V3_0/vhdl/
113	Matthias Grunewald's bug fixes: Branch and compare instructions didn't interpret immediate as signed.	rhoads	7508d 08h	/plasma/tags/V3_0/vhdl/
112	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7508d 09h	/plasma/tags/V3_0/vhdl/
108	changed interrupt vector from 0x30 to 0x3c	rhoads	7782d 05h	/plasma/tags/V3_0/vhdl/
107	merged rising_edge(clk) statements	rhoads	7782d 05h	/plasma/tags/V3_0/vhdl/
106	better test mem_pause	rhoads	7785d 07h	/plasma/tags/V3_0/vhdl/
105	better test mem_pause	rhoads	7785d 07h	/plasma/tags/V3_0/vhdl/
103	shorten similation times	rhoads	7786d 06h	/plasma/tags/V3_0/vhdl/
102	permit testing mem_pause	rhoads	7786d 06h	/plasma/tags/V3_0/vhdl/
101	Correctly freeze the pipeline when mem_pause = '1'	rhoads	7786d 06h	/plasma/tags/V3_0/vhdl/
99	correct upper 32-bits for mult(-1,-1)	rhoads	7928d 06h	/plasma/tags/V3_0/vhdl/
98	Fix size of GENERIC ram.	rhoads	7933d 04h	/plasma/tags/V3_0/vhdl/
97	added documentation	rhoads	7997d 10h	/plasma/tags/V3_0/vhdl/
96	Simplify take_branch	rhoads	8031d 12h	/plasma/tags/V3_0/vhdl/
95	register mem_write and mem_byte_sel for speed calculations	rhoads	8031d 12h	/plasma/tags/V3_0/vhdl/
93	make run now runs for 500 us	rhoads	8033d 05h	/plasma/tags/V3_0/vhdl/
92	Updated	rhoads	8033d 05h	/plasma/tags/V3_0/vhdl/
91	Removed unused alu_function_type entries	rhoads	8033d 05h	/plasma/tags/V3_0/vhdl/
90	Now multiplies two bits at a time	rhoads	8033d 05h	/plasma/tags/V3_0/vhdl/

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[/] [plasma/] [tags/] [V3_0/] [vhdl/] - Rev 115

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