OpenCores
URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [tags/] [V3_0/] [vhdl/] - Rev 131

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
131 Changed "GENERIC" to "DEFAULT" to be Xilinx friendly. rhoads 7187d 22h /plasma/tags/V3_0/vhdl/
129 Added reset_in to sensitivity list rhoads 7206d 22h /plasma/tags/V3_0/vhdl/
128 Reset all registers, constants now upper case. rhoads 7325d 09h /plasma/tags/V3_0/vhdl/
125 Fixed pc_source_type comment. rhoads 7343d 23h /plasma/tags/V3_0/vhdl/
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7343d 23h /plasma/tags/V3_0/vhdl/
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7410d 23h /plasma/tags/V3_0/vhdl/
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7475d 00h /plasma/tags/V3_0/vhdl/
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7486d 12h /plasma/tags/V3_0/vhdl/
120 Make generics "GENERIC" rhoads 7486d 12h /plasma/tags/V3_0/vhdl/
119 Opcodes from count.c rhoads 7524d 23h /plasma/tags/V3_0/vhdl/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 23h /plasma/tags/V3_0/vhdl/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 23h /plasma/tags/V3_0/vhdl/
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 23h /plasma/tags/V3_0/vhdl/
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7524d 23h /plasma/tags/V3_0/vhdl/
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7524d 23h /plasma/tags/V3_0/vhdl/
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.
rhoads 7524d 23h /plasma/tags/V3_0/vhdl/
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 23h /plasma/tags/V3_0/vhdl/
108 changed interrupt vector from 0x30 to 0x3c rhoads 7798d 20h /plasma/tags/V3_0/vhdl/
107 merged rising_edge(clk) statements rhoads 7798d 20h /plasma/tags/V3_0/vhdl/
106 better test mem_pause rhoads 7801d 22h /plasma/tags/V3_0/vhdl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.