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[/] [plasma/] [trunk/] [vhdl/] - Rev 184

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Rev	Log message	Author	Age	Path
184	Fix comment	rhoads	6504d 17h	/plasma/trunk/vhdl/
181	Fix typo in comment	rhoads	6504d 18h	/plasma/trunk/vhdl/
180	Easily permit full UART simulation	rhoads	6504d 18h	/plasma/trunk/vhdl/
139	Major changes -- updated to Plasma Version 3	rhoads	6818d 14h	/plasma/trunk/vhdl/
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7298d 13h	/plasma/trunk/vhdl/
131	Changed "GENERIC" to "DEFAULT" to be Xilinx friendly.	rhoads	7298d 13h	/plasma/trunk/vhdl/
129	Added reset_in to sensitivity list	rhoads	7317d 13h	/plasma/trunk/vhdl/
128	Reset all registers, constants now upper case.	rhoads	7436d 00h	/plasma/trunk/vhdl/
125	Fixed pc_source_type comment.	rhoads	7454d 13h	/plasma/trunk/vhdl/
124	Holger Lohn's fix for interrupts when 3-state pipeline enabled.	rhoads	7454d 13h	/plasma/trunk/vhdl/
123	Uncomment out the Altera portion. Xilinx users may need to re-comment out this section.	rhoads	7521d 14h	/plasma/trunk/vhdl/
122	Added comment to explain why c_bus isn't delayed but reg_dest is delayed.	rhoads	7585d 14h	/plasma/trunk/vhdl/
121	Added Matthias Gruenewald's tri-state area-optimized option	rhoads	7597d 03h	/plasma/trunk/vhdl/
120	Make generics "GENERIC"	rhoads	7597d 03h	/plasma/trunk/vhdl/
119	Opcodes from count.c	rhoads	7635d 14h	/plasma/trunk/vhdl/
118	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7635d 14h	/plasma/trunk/vhdl/
117	Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7635d 14h	/plasma/trunk/vhdl/
116	Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7635d 14h	/plasma/trunk/vhdl/
115	Matthias Grunewald's changes for Xilinx FPGA dual-port RAM.	rhoads	7635d 14h	/plasma/trunk/vhdl/
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7635d 14h	/plasma/trunk/vhdl/

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[/] [plasma/] [trunk/] [vhdl/] - Rev 184

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