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[/] [plasma/] [trunk/] [vhdl/] - Rev 203

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Rev	Log message	Author	Age	Path
203	Fixed stages comment	rhoads	6318d 19h	/plasma/trunk/vhdl/
202	Defined outputing PC as stage #0	rhoads	6318d 19h	/plasma/trunk/vhdl/
196	Explained how to remove mult.vhd and use SW multiplication and division.	rhoads	6366d 11h	/plasma/trunk/vhdl/
194	Implemented BREAK and SYSCALL opcodes	rhoads	6383d 15h	/plasma/trunk/vhdl/
186	Change memory_type to "XILINX_16X"	rhoads	6400d 08h	/plasma/trunk/vhdl/
185	Latest opcodes from count.c	rhoads	6415d 11h	/plasma/trunk/vhdl/
184	Fix comment	rhoads	6415d 11h	/plasma/trunk/vhdl/
181	Fix typo in comment	rhoads	6415d 12h	/plasma/trunk/vhdl/
180	Easily permit full UART simulation	rhoads	6415d 12h	/plasma/trunk/vhdl/
139	Major changes -- updated to Plasma Version 3	rhoads	6729d 08h	/plasma/trunk/vhdl/
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7209d 07h	/plasma/trunk/vhdl/
131	Changed "GENERIC" to "DEFAULT" to be Xilinx friendly.	rhoads	7209d 07h	/plasma/trunk/vhdl/
129	Added reset_in to sensitivity list	rhoads	7228d 07h	/plasma/trunk/vhdl/
128	Reset all registers, constants now upper case.	rhoads	7346d 18h	/plasma/trunk/vhdl/
125	Fixed pc_source_type comment.	rhoads	7365d 07h	/plasma/trunk/vhdl/
124	Holger Lohn's fix for interrupts when 3-state pipeline enabled.	rhoads	7365d 07h	/plasma/trunk/vhdl/
123	Uncomment out the Altera portion. Xilinx users may need to re-comment out this section.	rhoads	7432d 08h	/plasma/trunk/vhdl/
122	Added comment to explain why c_bus isn't delayed but reg_dest is delayed.	rhoads	7496d 08h	/plasma/trunk/vhdl/
121	Added Matthias Gruenewald's tri-state area-optimized option	rhoads	7507d 21h	/plasma/trunk/vhdl/
120	Make generics "GENERIC"	rhoads	7507d 21h	/plasma/trunk/vhdl/

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[/] [plasma/] [trunk/] [vhdl/] - Rev 203

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