URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] - Rev 369

Rev	Log message	Author	Age	Path
369	Simplify E_RX_CLK usage	rhoads	5497d 21h	/plasma/trunk/vhdl/
365	Added UNISIM comment	rhoads	5555d 22h	/plasma/trunk/vhdl/
356	Added space to align text	rhoads	5607d 21h	/plasma/trunk/vhdl/
352		linus	5656d 14h	/plasma/trunk/vhdl/
350		root	5685d 09h	/plasma/trunk/vhdl/
348	Added comment for 32MB and 128MB DDR parts	rhoads	5716d 05h	/plasma/trunk/vhdl/
347	Xilinx ISE Project file	rhoads	5716d 05h	/plasma/trunk/vhdl/
346	Support optional 4KB cache	rhoads	5753d 05h	/plasma/trunk/vhdl/
345	Commented out optional mult speedup	rhoads	5757d 01h	/plasma/trunk/vhdl/
344	Fixed compiler warning	rhoads	5757d 01h	/plasma/trunk/vhdl/
343	Initial working cache	rhoads	5757d 01h	/plasma/trunk/vhdl/
337	Initial attempt at a cache	rhoads	5762d 06h	/plasma/trunk/vhdl/
335	Use enable signal for byte_we	rhoads	5804d 00h	/plasma/trunk/vhdl/
334	Short time for averaging read signal for 12.5 MHz case	rhoads	5813d 23h	/plasma/trunk/vhdl/
333	Updated Altera lpm_ram_dp usage for Cyclone FPGAs	rhoads	5813d 23h	/plasma/trunk/vhdl/
332	Updated Altera lpm_ram_dp	rhoads	5813d 23h	/plasma/trunk/vhdl/
331	Commented out unconnected signals	rhoads	5875d 00h	/plasma/trunk/vhdl/
329	Fix interrupt line comment	rhoads	5965d 22h	/plasma/trunk/vhdl/
288	Added Ethernet MAC with DMA	rhoads	6092d 22h	/plasma/trunk/vhdl/
287	Added ethernet and flash control	rhoads	6092d 22h	/plasma/trunk/vhdl/