URL https://opencores.org/ocsvn/plasma/plasma/trunk

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[/] [plasma/] [trunk/] [vhdl/] - Rev 371

Rev	Log message	Author	Age	Path
371		rhoads	5435d 22h	/plasma/trunk/vhdl/
370	Fix "SLTIU v0, a0, -4000" by making imm signed	rhoads	5435d 23h	/plasma/trunk/vhdl/
369	Simplify E_RX_CLK usage	rhoads	5441d 10h	/plasma/trunk/vhdl/
365	Added UNISIM comment	rhoads	5499d 11h	/plasma/trunk/vhdl/
356	Added space to align text	rhoads	5551d 10h	/plasma/trunk/vhdl/
352		linus	5600d 03h	/plasma/trunk/vhdl/
350		root	5628d 22h	/plasma/trunk/vhdl/
348	Added comment for 32MB and 128MB DDR parts	rhoads	5659d 17h	/plasma/trunk/vhdl/
347	Xilinx ISE Project file	rhoads	5659d 18h	/plasma/trunk/vhdl/
346	Support optional 4KB cache	rhoads	5696d 17h	/plasma/trunk/vhdl/
345	Commented out optional mult speedup	rhoads	5700d 14h	/plasma/trunk/vhdl/
344	Fixed compiler warning	rhoads	5700d 14h	/plasma/trunk/vhdl/
343	Initial working cache	rhoads	5700d 14h	/plasma/trunk/vhdl/
337	Initial attempt at a cache	rhoads	5705d 18h	/plasma/trunk/vhdl/
335	Use enable signal for byte_we	rhoads	5747d 12h	/plasma/trunk/vhdl/
334	Short time for averaging read signal for 12.5 MHz case	rhoads	5757d 12h	/plasma/trunk/vhdl/
333	Updated Altera lpm_ram_dp usage for Cyclone FPGAs	rhoads	5757d 12h	/plasma/trunk/vhdl/
332	Updated Altera lpm_ram_dp	rhoads	5757d 12h	/plasma/trunk/vhdl/
331	Commented out unconnected signals	rhoads	5818d 12h	/plasma/trunk/vhdl/
329	Fix interrupt line comment	rhoads	5909d 11h	/plasma/trunk/vhdl/