URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] - Rev 377

Rev	Log message	Author	Age	Path
377	Fix cache_we warning	rhoads	5226d 09h	/plasma/trunk/vhdl/
376	Add write_enable to sensitivity list for Altera	rhoads	5226d 10h	/plasma/trunk/vhdl/
374	Fixed comment	rhoads	5271d 23h	/plasma/trunk/vhdl/
371		rhoads	5421d 12h	/plasma/trunk/vhdl/
370	Fix "SLTIU v0, a0, -4000" by making imm signed	rhoads	5421d 13h	/plasma/trunk/vhdl/
369	Simplify E_RX_CLK usage	rhoads	5427d 00h	/plasma/trunk/vhdl/
365	Added UNISIM comment	rhoads	5485d 01h	/plasma/trunk/vhdl/
356	Added space to align text	rhoads	5537d 00h	/plasma/trunk/vhdl/
352		linus	5585d 17h	/plasma/trunk/vhdl/
350		root	5614d 12h	/plasma/trunk/vhdl/
348	Added comment for 32MB and 128MB DDR parts	rhoads	5645d 08h	/plasma/trunk/vhdl/
347	Xilinx ISE Project file	rhoads	5645d 08h	/plasma/trunk/vhdl/
346	Support optional 4KB cache	rhoads	5682d 07h	/plasma/trunk/vhdl/
345	Commented out optional mult speedup	rhoads	5686d 04h	/plasma/trunk/vhdl/
344	Fixed compiler warning	rhoads	5686d 04h	/plasma/trunk/vhdl/
343	Initial working cache	rhoads	5686d 04h	/plasma/trunk/vhdl/
337	Initial attempt at a cache	rhoads	5691d 08h	/plasma/trunk/vhdl/
335	Use enable signal for byte_we	rhoads	5733d 03h	/plasma/trunk/vhdl/
334	Short time for averaging read signal for 12.5 MHz case	rhoads	5743d 02h	/plasma/trunk/vhdl/
333	Updated Altera lpm_ram_dp usage for Cyclone FPGAs	rhoads	5743d 02h	/plasma/trunk/vhdl/