URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] - Rev 384

Rev	Log message	Author	Age	Path
383	Permit up to 64KB internal RAM and updated cache code.	rhoads	5070d 19h	/plasma/trunk/vhdl/
377	Fix cache_we warning	rhoads	5214d 01h	/plasma/trunk/vhdl/
376	Add write_enable to sensitivity list for Altera	rhoads	5214d 03h	/plasma/trunk/vhdl/
374	Fixed comment	rhoads	5259d 16h	/plasma/trunk/vhdl/
371		rhoads	5409d 05h	/plasma/trunk/vhdl/
370	Fix "SLTIU v0, a0, -4000" by making imm signed	rhoads	5409d 05h	/plasma/trunk/vhdl/
369	Simplify E_RX_CLK usage	rhoads	5414d 17h	/plasma/trunk/vhdl/
365	Added UNISIM comment	rhoads	5472d 17h	/plasma/trunk/vhdl/
356	Added space to align text	rhoads	5524d 16h	/plasma/trunk/vhdl/
352		linus	5573d 09h	/plasma/trunk/vhdl/
350		root	5602d 05h	/plasma/trunk/vhdl/
348	Added comment for 32MB and 128MB DDR parts	rhoads	5633d 00h	/plasma/trunk/vhdl/
347	Xilinx ISE Project file	rhoads	5633d 00h	/plasma/trunk/vhdl/
346	Support optional 4KB cache	rhoads	5670d 00h	/plasma/trunk/vhdl/
345	Commented out optional mult speedup	rhoads	5673d 20h	/plasma/trunk/vhdl/
344	Fixed compiler warning	rhoads	5673d 20h	/plasma/trunk/vhdl/
343	Initial working cache	rhoads	5673d 21h	/plasma/trunk/vhdl/
337	Initial attempt at a cache	rhoads	5679d 01h	/plasma/trunk/vhdl/
335	Use enable signal for byte_we	rhoads	5720d 19h	/plasma/trunk/vhdl/
334	Short time for averaging read signal for 12.5 MHz case	rhoads	5730d 19h	/plasma/trunk/vhdl/