OpenCores
URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] - Rev 430

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
429 Changed INIT bit length in RAM16X1D and RAM32X1D rhoads 3987d 18h /plasma/trunk/vhdl/
428 Fix mult bugs "0*-1" and "-5%12". rhoads 4002d 23h /plasma/trunk/vhdl/
404 Changed spacing rhoads 4740d 14h /plasma/trunk/vhdl/
403 Disable Ethernet and cache when simulating. rhoads 4740d 14h /plasma/trunk/vhdl/
397 Added RAM32X1D option rhoads 4874d 08h /plasma/trunk/vhdl/
391 Better fix for 0x8000000 * negative number rhoads 5026d 14h /plasma/trunk/vhdl/
390 Handle special case of signed mult of 0x80000000 and a negative number rhoads 5029d 13h /plasma/trunk/vhdl/
383 Permit up to 64KB internal RAM and updated cache code. rhoads 5036d 14h /plasma/trunk/vhdl/
377 Fix cache_we warning rhoads 5179d 20h /plasma/trunk/vhdl/
376 Add write_enable to sensitivity list for Altera rhoads 5179d 21h /plasma/trunk/vhdl/
374 Fixed comment rhoads 5225d 10h /plasma/trunk/vhdl/
371 rhoads 5374d 23h /plasma/trunk/vhdl/
370 Fix "SLTIU v0, a0, -4000" by making imm signed rhoads 5375d 00h /plasma/trunk/vhdl/
369 Simplify E_RX_CLK usage rhoads 5380d 11h /plasma/trunk/vhdl/
365 Added UNISIM comment rhoads 5438d 12h /plasma/trunk/vhdl/
356 Added space to align text rhoads 5490d 11h /plasma/trunk/vhdl/
352 linus 5539d 04h /plasma/trunk/vhdl/
350 root 5567d 23h /plasma/trunk/vhdl/
348 Added comment for 32MB and 128MB DDR parts rhoads 5598d 19h /plasma/trunk/vhdl/
347 Xilinx ISE Project file rhoads 5598d 19h /plasma/trunk/vhdl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.