OpenCores
URL https://opencores.org/ocsvn/pltbutils/pltbutils/trunk

Subversion Repositories pltbutils

[/] [pltbutils/] [branches/] [dev_beta0002/] [src/] [vhdl/] - Rev 21

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
21 alpha0005 - pltbutils_user_cfg_pkg.vhd: First commit. pela 3801d 19h /pltbutils/branches/dev_beta0002/src/vhdl/
18 alpha0004 - pltbutils_func_pkg.vhd:
Corrected returned ranges from to_ascending() and to_descending(), to make them work with vectors where the lowest bit does not have number 0.
pela 3834d 12h /pltbutils/branches/dev_beta0002/src/vhdl/
14 alpha0003 - pltbutils_func_pkg.vhd:
Added functions to_ascending(), to_descending() and hxstr().
check() now outputs hexadecimal values instead of binary for std_logic_vector, unsigned and signed.
pela 3835d 10h /pltbutils/branches/dev_beta0002/src/vhdl/
8 alpha0002 - pltbutils_comp_pkg.vhd: Added inverted clock output and a generic for setting initial value to pltbutils_clkgen. pela 3857d 11h /pltbutils/branches/dev_beta0002/src/vhdl/
7 alpha0002 - pltbutils_comp.vhd: Added inverted clock output and a generic for setting initial value to pltbutils_clkgen. pela 3857d 11h /pltbutils/branches/dev_beta0002/src/vhdl/
6 alpha0002 - pltbutils_func_pkg.vhd: Added overloaded print procedures with boolean argument called active, which is useful for debug switches, etc.
Added overloaded procedures waitsig().
pela 3857d 11h /pltbutils/branches/dev_beta0002/src/vhdl/
5 alpha0002 - pltbutils_files.lst: Removed file paths. pela 3857d 11h /pltbutils/branches/dev_beta0002/src/vhdl/
2 First commit. pela 3926d 12h /pltbutils/branches/dev_beta0002/src/vhdl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.