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[/] [potato/] - Rev 26

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Rev	Log message	Author	Age	Path
26	Prevent exceptions from being taken while stalling Jumping to an exception handler while stalling and waiting for a load/store instruction to finish can cause undefined results from the load/store instruction. This actually fixes the issue mentioned in revision r20.	skordal	3290d 15h	/potato/
25	Add placeholder cache modules and a wishbone arbiter	skordal	3292d 19h	/potato/
24	Remove unused STRINGIFY macros	skordal	3293d 08h	/potato/
23	Create branch to use for implementing a cache	skordal	3293d 08h	/potato/
22	Fix the potato_get_badvaddr() macro	skordal	3293d 09h	/potato/
21	Upgrade the example design to use a 60 MHz system clock	skordal	3293d 09h	/potato/
20	Fix SHA256 benchmark crash by storing all registers on exception handler entry This problem will disappear when the processor is updated to conform to the new supervisor specification, which will allow us to use a compiler that conforms to the new "official" ABI.	skordal	3293d 09h	/potato/
19	SHA256 benchmark: allow compiler to inline at will	skordal	3293d 09h	/potato/
18	instr_misalign_check: add do_jump to sensitivity list	skordal	3295d 09h	/potato/
17	Improve detection of unaligned instructions	skordal	3299d 16h	/potato/
16	Correct grammar in source code comment	skordal	3299d 16h	/potato/
15	SHA256 benchmark: fix Makefile syntax error	skordal	3306d 09h	/potato/
14	Improve detection of invalid instructions	skordal	3306d 10h	/potato/
13	Add SHA256 benchmark code	skordal	3306d 14h	/potato/
12	Update example design with correct bug-report URL and testbenches	skordal	3306d 16h	/potato/
11	Correct FIFO file header	skordal	3306d 17h	/potato/
10	Add missing FIFO module	skordal	3311d 11h	/potato/
9	Remove dependency on a non-existent target in the Makefile	skordal	3311d 11h	/potato/
8	Clarify instruction ROM naming in the example design README	skordal	3318d 13h	/potato/
7	Add test design for the Nexys 4 board from Digilent	skordal	3318d 13h	/potato/

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[/] [potato/] - Rev 26

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