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Rev Log message Author Age Path
35 Prevent jumping/branching when stalling skordal 3288d 22h /potato/
34 Prevent flushing the pipeline if it is stalling skordal 3288d 22h /potato/
33 Ensure correct read of CSR after stall skordal 3288d 22h /potato/
32 Prevent jumping/branching when stalling skordal 3291d 19h /potato/
31 Prevent flushing the pipeline if it is stalling skordal 3291d 20h /potato/
30 Add testcase for a combination of instructions that fail when using cache skordal 3294d 01h /potato/
29 Add reset functionality for the WB arbiter state machine skordal 3296d 20h /potato/
28 Add rudimentary User's manual skordal 3302d 19h /potato/
27 Prevent exceptions from being taken while stalling skordal 3302d 21h /potato/
26 Prevent exceptions from being taken while stalling

Jumping to an exception handler while stalling and waiting for a load/store
instruction to finish can cause undefined results from the load/store
instruction. This actually fixes the issue mentioned in revision r20.
skordal 3303d 00h /potato/
25 Add placeholder cache modules and a wishbone arbiter skordal 3305d 05h /potato/
24 Remove unused STRINGIFY macros skordal 3305d 18h /potato/
23 Create branch to use for implementing a cache skordal 3305d 18h /potato/
22 Fix the potato_get_badvaddr() macro skordal 3305d 18h /potato/
21 Upgrade the example design to use a 60 MHz system clock skordal 3305d 19h /potato/
20 Fix SHA256 benchmark crash by storing all registers on exception handler entry

This problem will disappear when the processor is updated to conform to the
new supervisor specification, which will allow us to use a compiler that
conforms to the new "official" ABI.
skordal 3305d 19h /potato/
19 SHA256 benchmark: allow compiler to inline at will skordal 3305d 19h /potato/
18 instr_misalign_check: add do_jump to sensitivity list skordal 3307d 19h /potato/
17 Improve detection of unaligned instructions skordal 3312d 02h /potato/
16 Correct grammar in source code comment skordal 3312d 02h /potato/

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