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Rev Log message Author Age Path
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3291d 00h /potato/
41 Make continouous status register reads asynchronous skordal 3291d 00h /potato/
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.		 skordal 3291d 00h /potato/
39 Disable IRQs when handling exceptions skordal 3291d 00h /potato/
38 Add "Hello World" test application skordal 3291d 01h /potato/
37 Add macro to set the TOHOST register from C code skordal 3291d 01h /potato/
36 Ensure correct read of CSR after stall skordal 3291d 01h /potato/
35 Prevent jumping/branching when stalling skordal 3291d 01h /potato/
34 Prevent flushing the pipeline if it is stalling skordal 3291d 01h /potato/
33 Ensure correct read of CSR after stall skordal 3291d 01h /potato/
32 Prevent jumping/branching when stalling skordal 3293d 22h /potato/
31 Prevent flushing the pipeline if it is stalling skordal 3293d 23h /potato/
30 Add testcase for a combination of instructions that fail when using cache skordal 3296d 04h /potato/
29 Add reset functionality for the WB arbiter state machine skordal 3298d 23h /potato/
28 Add rudimentary User's manual skordal 3304d 22h /potato/
27 Prevent exceptions from being taken while stalling skordal 3305d 00h /potato/
26 Prevent exceptions from being taken while stalling

Jumping to an exception handler while stalling and waiting for a load/store
instruction to finish can cause undefined results from the load/store
instruction. This actually fixes the issue mentioned in revision r20.		 skordal 3305d 03h /potato/
25 Add placeholder cache modules and a wishbone arbiter skordal 3307d 08h /potato/
24 Remove unused STRINGIFY macros skordal 3307d 21h /potato/
23 Create branch to use for implementing a cache skordal 3307d 21h /potato/

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