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Rev Log message Author Age Path
44 Add instruction cache and use the WB adapter as dmem interface skordal 3425d 00h /potato/branches/
43 Improve instruction fetch logic skordal 3425d 00h /potato/branches/
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3425d 00h /potato/branches/
41 Make continouous status register reads asynchronous skordal 3425d 00h /potato/branches/
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.		 skordal 3425d 00h /potato/branches/
39 Disable IRQs when handling exceptions skordal 3425d 00h /potato/branches/
38 Add "Hello World" test application skordal 3425d 01h /potato/branches/
37 Add macro to set the TOHOST register from C code skordal 3425d 01h /potato/branches/
33 Ensure correct read of CSR after stall skordal 3425d 01h /potato/branches/
32 Prevent jumping/branching when stalling skordal 3427d 23h /potato/branches/
31 Prevent flushing the pipeline if it is stalling skordal 3428d 00h /potato/branches/
30 Add testcase for a combination of instructions that fail when using cache skordal 3430d 04h /potato/branches/
29 Add reset functionality for the WB arbiter state machine skordal 3432d 23h /potato/branches/
27 Prevent exceptions from being taken while stalling skordal 3439d 01h /potato/branches/
25 Add placeholder cache modules and a wishbone arbiter skordal 3441d 08h /potato/branches/
23 Create branch to use for implementing a cache skordal 3441d 21h /potato/branches/
1 The project and the structure was created root 3480d 13h /potato/branches/

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