OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [tags/] [v0.1/] - Rev 28

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
28 Add rudimentary User's manual skordal 3402d 08h /potato/tags/v0.1/
26 Prevent exceptions from being taken while stalling

Jumping to an exception handler while stalling and waiting for a load/store
instruction to finish can cause undefined results from the load/store
instruction. This actually fixes the issue mentioned in revision r20.		 skordal 3402d 13h /potato/tags/v0.1/
24 Remove unused STRINGIFY macros skordal 3405d 07h /potato/tags/v0.1/
22 Fix the potato_get_badvaddr() macro skordal 3405d 07h /potato/tags/v0.1/
21 Upgrade the example design to use a 60 MHz system clock skordal 3405d 08h /potato/tags/v0.1/
20 Fix SHA256 benchmark crash by storing all registers on exception handler entry

This problem will disappear when the processor is updated to conform to the
new supervisor specification, which will allow us to use a compiler that
conforms to the new "official" ABI.		 skordal 3405d 08h /potato/tags/v0.1/
19 SHA256 benchmark: allow compiler to inline at will skordal 3405d 08h /potato/tags/v0.1/
18 instr_misalign_check: add do_jump to sensitivity list skordal 3407d 08h /potato/tags/v0.1/
17 Improve detection of unaligned instructions skordal 3411d 15h /potato/tags/v0.1/
16 Correct grammar in source code comment skordal 3411d 15h /potato/tags/v0.1/
15 SHA256 benchmark: fix Makefile syntax error skordal 3418d 08h /potato/tags/v0.1/
14 Improve detection of invalid instructions skordal 3418d 08h /potato/tags/v0.1/
13 Add SHA256 benchmark code skordal 3418d 13h /potato/tags/v0.1/
12 Update example design with correct bug-report URL and testbenches skordal 3418d 15h /potato/tags/v0.1/
11 Correct FIFO file header skordal 3418d 15h /potato/tags/v0.1/
10 Add missing FIFO module skordal 3423d 09h /potato/tags/v0.1/
9 Remove dependency on a non-existent target in the Makefile skordal 3423d 09h /potato/tags/v0.1/
8 Clarify instruction ROM naming in the example design README skordal 3430d 11h /potato/tags/v0.1/
7 Add test design for the Nexys 4 board from Digilent skordal 3430d 12h /potato/tags/v0.1/
6 Add ISA tests skordal 3430d 12h /potato/tags/v0.1/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.