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[/] [ps2/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 51

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Rev Log message Author Age Path
51 New directory structure. root 5664d 04h /ps2/tags/asyst_2/rtl/verilog/
30 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7610d 18h /ps2/tags/asyst_2/rtl/verilog/
29 small modifications. gorand 7610d 18h /ps2/tags/asyst_2/rtl/verilog/
27 added 8-bit access to divider register. gorand 7614d 18h /ps2/tags/asyst_2/rtl/verilog/
25 unit delay on registers added primozs 7649d 01h /ps2/tags/asyst_2/rtl/verilog/
24 support for configurable devider added primozs 7649d 02h /ps2/tags/asyst_2/rtl/verilog/
23 Added an option to use constant values instead of RAM
in the translation table.		 mihad 7743d 00h /ps2/tags/asyst_2/rtl/verilog/
21 Error fixed again. simons 7743d 21h /ps2/tags/asyst_2/rtl/verilog/
19 Error fixed. simons 7743d 21h /ps2/tags/asyst_2/rtl/verilog/
17 resetall keyword removed. ifdef moved to a separated line. simons 7771d 19h /ps2/tags/asyst_2/rtl/verilog/
15 Change the address width. simons 7776d 20h /ps2/tags/asyst_2/rtl/verilog/
13 Added mouse interface and everything for its handling, cleaned up some unused code mihad 8190d 23h /ps2/tags/asyst_2/rtl/verilog/
9 Added one more ps2 state machine for mouse interface mihad 8190d 23h /ps2/tags/asyst_2/rtl/verilog/
7 Little/big endian changes continued mihad 8238d 20h /ps2/tags/asyst_2/rtl/verilog/
6 Little/big endian changes incorporated mihad 8238d 21h /ps2/tags/asyst_2/rtl/verilog/
5 One bug fixed mihad 8240d 18h /ps2/tags/asyst_2/rtl/verilog/
4 Changed defines for simulation to work without xilinx primitives mihad 8240d 20h /ps2/tags/asyst_2/rtl/verilog/
2 Initial project import - working mihad 8240d 20h /ps2/tags/asyst_2/rtl/verilog/

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