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[/] [ps2/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 51

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Rev Log message Author Age Path
51 New directory structure. root 5601d 12h /ps2/tags/rel_12/rtl/verilog/
40 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7529d 07h /ps2/tags/rel_12/rtl/verilog/
29 small modifications. gorand 7548d 02h /ps2/tags/rel_12/rtl/verilog/
27 added 8-bit access to divider register. gorand 7552d 02h /ps2/tags/rel_12/rtl/verilog/
25 unit delay on registers added primozs 7586d 09h /ps2/tags/rel_12/rtl/verilog/
24 support for configurable devider added primozs 7586d 10h /ps2/tags/rel_12/rtl/verilog/
23 Added an option to use constant values instead of RAM
in the translation table.		 mihad 7680d 08h /ps2/tags/rel_12/rtl/verilog/
21 Error fixed again. simons 7681d 05h /ps2/tags/rel_12/rtl/verilog/
19 Error fixed. simons 7681d 05h /ps2/tags/rel_12/rtl/verilog/
17 resetall keyword removed. ifdef moved to a separated line. simons 7709d 04h /ps2/tags/rel_12/rtl/verilog/
15 Change the address width. simons 7714d 04h /ps2/tags/rel_12/rtl/verilog/
13 Added mouse interface and everything for its handling, cleaned up some unused code mihad 8128d 07h /ps2/tags/rel_12/rtl/verilog/
9 Added one more ps2 state machine for mouse interface mihad 8128d 08h /ps2/tags/rel_12/rtl/verilog/
7 Little/big endian changes continued mihad 8176d 04h /ps2/tags/rel_12/rtl/verilog/
6 Little/big endian changes incorporated mihad 8176d 05h /ps2/tags/rel_12/rtl/verilog/
5 One bug fixed mihad 8178d 03h /ps2/tags/rel_12/rtl/verilog/
4 Changed defines for simulation to work without xilinx primitives mihad 8178d 04h /ps2/tags/rel_12/rtl/verilog/
2 Initial project import - working mihad 8178d 04h /ps2/tags/rel_12/rtl/verilog/

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