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[/] [ps2/] [tags/] [rel_8/] [rtl/] [verilog/] - Rev 25

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Rev Log message Author Age Path
25 unit delay on registers added primozs 7593d 06h /ps2/tags/rel_8/rtl/verilog/
24 support for configurable devider added primozs 7593d 07h /ps2/tags/rel_8/rtl/verilog/
23 Added an option to use constant values instead of RAM
in the translation table.
mihad 7687d 05h /ps2/tags/rel_8/rtl/verilog/
21 Error fixed again. simons 7688d 02h /ps2/tags/rel_8/rtl/verilog/
19 Error fixed. simons 7688d 02h /ps2/tags/rel_8/rtl/verilog/
17 resetall keyword removed. ifdef moved to a separated line. simons 7716d 00h /ps2/tags/rel_8/rtl/verilog/
15 Change the address width. simons 7721d 01h /ps2/tags/rel_8/rtl/verilog/
13 Added mouse interface and everything for its handling, cleaned up some unused code mihad 8135d 04h /ps2/tags/rel_8/rtl/verilog/
9 Added one more ps2 state machine for mouse interface mihad 8135d 04h /ps2/tags/rel_8/rtl/verilog/
7 Little/big endian changes continued mihad 8183d 01h /ps2/tags/rel_8/rtl/verilog/
6 Little/big endian changes incorporated mihad 8183d 02h /ps2/tags/rel_8/rtl/verilog/
5 One bug fixed mihad 8184d 23h /ps2/tags/rel_8/rtl/verilog/
4 Changed defines for simulation to work without xilinx primitives mihad 8185d 01h /ps2/tags/rel_8/rtl/verilog/
2 Initial project import - working mihad 8185d 01h /ps2/tags/rel_8/rtl/verilog/

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