OpenCores

URL https://opencores.org/ocsvn/qspiflash/qspiflash/trunk

Subversion Repositories qspiflash

[/] [qspiflash/] [trunk/] [bench/] - Rev 17

Go to most recent revision

Filtering Options

Rev	Log message	Author	Age	Path
17	Added an option to turn off verbose outputs per tick	dgisselq	2577d 10h	/qspiflash/trunk/bench/
16	Added a full blown test bench to the controller This includes: - A global make file, and a "make test" which will build the test bench. - Merging other versions of the QSPI flash driver I had lying around - Grabbing the best of these, and verifying that they work - The result is a reduction in overall logic	dgisselq	2719d 15h	/qspiflash/trunk/bench/
15	Made the flash simulator's size variable. Also adjusted the C interface, providing some new functions, so that the flash simulation can be loaded and queried easier.	dgisselq	2740d 21h	/qspiflash/trunk/bench/
14	Updates: little-big endian, various other fixes 1. Made the wbqspiflash.v and llqspi.v files compile with default_nettype none 2. Changed the internal flash representation to big endian. A little-big endian conversion is now required when writing to the flash from a PC. 3. Simplified the address description via w_wb_addr and w_spif_addr, so that the core is more flexible when changing sizes. 4. Removed the dependence upon the WB_CYC line ... as part of the WB simplifications I've been doing. 5. Got XIP working for the EQSPI flash (I guess --- it's been a while since I made those changes) 6. Adjusted (fixed) sim of read/writes to the volatile config register (necessary for XIP)	dgisselq	2740d 21h	/qspiflash/trunk/bench/
13	Fixed VERILATOR_ROOT static dependency.	dgisselq	2943d 11h	/qspiflash/trunk/bench/
12	Adding the sources for the extended Quad SPI flash test bench.	dgisselq	3010d 13h	/qspiflash/trunk/bench/
9	Minor changes to the baseline, FIRST RELEASE OF THE EQSPIFLASH controller!!	dgisselq	3027d 12h	/qspiflash/trunk/bench/
8	Minor documentation edits.	dgisselq	3258d 09h	/qspiflash/trunk/bench/
4	FIXED: in the previous version, the first read of the device would always fail. This was due to the fact that the Xilinx loader that read from the device to load the Xilinx configuration left the Quad SPI flash chip in a high data rate state. Thus, on reset, the first thing this core does it to take the device out of the high data rate state. Also, on a bus action waiting on a write to complete, the timing was off. This has now been corrected. Reads (in both modes) should now stall the bus (properly) while a write/erase cycle is ongoing, and complete when finished. The bug in high speed writing was traced to a read bug, not a write bug. High speed (i.e. 4-bit transaction) writing has been re-enabled. The bug in transitioning from 1-bit mode to 4-bit reads has been fixed. This was causing the high speed write bug mentioned above. Read ID was stalling the bus. This was traced to a sign error while referencing the chip select line, and has been fixed. The lowerlevel QSPI project was modified to add a holding state. We were struggling with a bug whereby a late read would hang the device. The upper level driver would issue it when the lower level driver was busy, and yet think that it was accomplished. The lower level driver was moving from ready to idle, so it never saw the read. Now, hold keeps the lower level driver in the ready state at the end of a read until the bus transaction is complete, or until it goes on to some other transaction other than reading data. (This was a big change.) Finally, unnecessary debugging lines were disabled in the simulator.	dgisselq	3458d 16h	/qspiflash/trunk/bench/
3	This quick update fixes some oopses associated with the original release. Specifically, I made sure the license comments were available in all source files, made sure all source files mentioned that they were a part of a Quad SPI flash controller, rather than the Basys-3 development board project they were originally a part of or the Spartan 3E project before that, I took out the (undocumented) debug "scaffolding" that was still in the Verilog files, and I added the C++ source for the bench test/simulator into the project. Although the full bench test is not complete, it should be sufficient for anyone who would wish to test this within Verilator. These changes should not affect any of the functionality of the core.	dgisselq	3465d 08h	/qspiflash/trunk/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.