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212 DPC changes\n\n\t+ established the DCS system rather than the UCA definitively\n\t+ Rather than usign 4 result queues now theres just a single one, of course 4 times wider, this was made to gain simplicity when writing and reading the RTL description that adapts this 4/3/1 word wide result buffer output into a 1 word wide result buffer input\n\t+ Added the Q1 queue to syncrhonize magnitude and normalization ops, managing them to enter at the sime tame rather than different times, formerly it was implemented by setting the normalization and magnitude results into the results buffers at 25th beat and 20th beat respectively, now both results enter into THE SINGLE RESULT QUEUE at 25th beat. This change also forces that Dot product operation to use the Q1 hardware and entering also at beath 25th into the result queue, it could be done in an earlier beatt (in fact in the 19th) but multiplexation logic would have to be added. jguarin2002 4373d 04h /raytrac/
211 Raytrac Beta 0.1 with Avalon MM Master & Avalon MM Slave Interfaces. Done\! jguarin2002 4373d 04h /raytrac/
210 Document advance..... towards dma oriented raytrac jguarin2002 4384d 17h /raytrac/
209 Working towards a DMA oriented RayTRac jguarin2002 4384d 17h /raytrac/
208 Working towards a DMA oriented RayTRac jguarin2002 4384d 17h /raytrac/
207 Working towards a DMA oriented RayTRac jguarin2002 4384d 17h /raytrac/
206 Working towards a DMA oriented RayTRac jguarin2002 4384d 17h /raytrac/
205 Working towards a DMA oriented RayTRac jguarin2002 4384d 17h /raytrac/
204 Working towards a DMA oriented RayTRac jguarin2002 4384d 17h /raytrac/
203 Working towards a DMA oriented RayTRac jguarin2002 4384d 17h /raytrac/
202 Working towards a DMA oriented RayTRac jguarin2002 4384d 17h /raytrac/
201 files no longer needed im.vhd and fadd32long.vhd jguarin2002 4384d 17h /raytrac/
200 raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers jguarin2002 4384d 18h /raytrac/
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4400d 23h /raytrac/
198 Check out for the best out for the best organization so the datapath does not consume to many logic cells jguarin2002 4400d 23h /raytrac/
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4411d 00h /raytrac/
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4414d 12h /raytrac/
195 Document advance and changes in the design jguarin2002 4417d 08h /raytrac/
194 Work In Progress jguarin2002 4432d 14h /raytrac/
193 WIP: Main Document jguarin2002 4433d 11h /raytrac/

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