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Rev Log message Author Age Path
85 get doesnt fit anymore... jguarin2002 4770d 09h /raytrac/
84 Floating Point Adders: (ema3,add3) is an a+b+c adder and (ema2,add2) is an a+b adder. Ema's are blocks to normalize the exponents and shift the mantissas as required, add's are blocks that make the mantissa addition and normalize the result again into a 32 bit IEEE float format jguarin2002 4770d 09h /raytrac/
83 Only to have it as an example of what to do to sign a mantissa jguarin2002 4770d 09h /raytrac/
82 FPBRANCH releaseeeesvn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd jguarin2002 4773d 04h /raytrac/
81 Almost There jguarin2002 4777d 02h /raytrac/
80 not a revision jguarin2002 4777d 18h /raytrac/
79 I can't use a 20 bits mantissa.... eliminating optimization jguarin2002 4781d 12h /raytrac/
78 Metamorphosis jguarin2002 4789d 01h /raytrac/
77 Now support for addition and substraction of A(7,10) component vectors jguarin2002 4789d 14h /raytrac/
76 Upgrade para obtener una mantissa de 20 bits jguarin2002 4791d 12h /raytrac/
75 Optimization done on matissa lenght for x**-1 and x**0.5, getting a longer mantissa of 20 bits instead one of 18 bits jguarin2002 4793d 07h /raytrac/
74 On the rush, correct chip floor planning problem jguarin2002 4798d 01h /raytrac/
73 Almost Ready Division and Square Root jguarin2002 4799d 06h /raytrac/
72 Minor changes, is more a matter of format rather than anything... jguarin2002 4799d 18h /raytrac/
71 RLshifterAlfa jguarin2002 4802d 11h /raytrac/
70 RLshifterbeta++ jguarin2002 4802d 11h /raytrac/
69 RLshifterbeta jguarin2002 4802d 13h /raytrac/
68 On the rush cant explain what I did, but sure its about sqrtdiv jguarin2002 4803d 01h /raytrac/
67 On the rush cant explain what I did, but sure its about sqrtdiv jguarin2002 4805d 03h /raytrac/
66 tb.vhd moved to testbench directory jguarin2002 4806d 15h /raytrac/

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