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[/] [raytrac/] - Rev 91

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Rev	Log message	Author	Age	Path
91	Optimizations made on ema2 and ema3: First One, ema3 and ema2 both now has a 4 pipeline, this equalization has saved lots of registers. Second One: Shifters to denormalize mantissas before addition are implemented with multipliers and inverting the bits direction in the bit vectors, resulting in a saving of resources of 332->253 LEs in ema2 (23% saving) and 608->408 LEs in ema3svn status (32% saving)	jguarin2002	4760d 11h	/raytrac/
90	Minor corrections to ema2 zero support	jguarin2002	4760d 18h	/raytrac/
89	floating point mult ready	jguarin2002	4760d 18h	/raytrac/
88	Exponent Managment Addition: supports now Zero	jguarin2002	4760d 20h	/raytrac/
87	For the sake of easyness, mmp is called now mul2	jguarin2002	4762d 20h	/raytrac/
86	For the sake of easyness, mmp is called now mul2	jguarin2002	4762d 20h	/raytrac/
85	get doesnt fit anymore...	jguarin2002	4763d 12h	/raytrac/
84	Floating Point Adders: (ema3,add3) is an a+b+c adder and (ema2,add2) is an a+b adder. Ema's are blocks to normalize the exponents and shift the mantissas as required, add's are blocks that make the mantissa addition and normalize the result again into a 32 bit IEEE float format	jguarin2002	4763d 12h	/raytrac/
83	Only to have it as an example of what to do to sign a mantissa	jguarin2002	4763d 12h	/raytrac/
82	FPBRANCH releaseeeesvn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd	jguarin2002	4766d 07h	/raytrac/
81	Almost There	jguarin2002	4770d 05h	/raytrac/
80	not a revision	jguarin2002	4770d 21h	/raytrac/
79	I can't use a 20 bits mantissa.... eliminating optimization	jguarin2002	4774d 15h	/raytrac/
78	Metamorphosis	jguarin2002	4782d 04h	/raytrac/
77	Now support for addition and substraction of A(7,10) component vectors	jguarin2002	4782d 17h	/raytrac/
76	Upgrade para obtener una mantissa de 20 bits	jguarin2002	4784d 15h	/raytrac/
75	Optimization done on matissa lenght for x-1 and x0.5, getting a longer mantissa of 20 bits instead one of 18 bits	jguarin2002	4786d 10h	/raytrac/
74	On the rush, correct chip floor planning problem	jguarin2002	4791d 04h	/raytrac/
73	Almost Ready Division and Square Root	jguarin2002	4792d 09h	/raytrac/
72	Minor changes, is more a matter of format rather than anything...	jguarin2002	4792d 21h	/raytrac/

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[/] [raytrac/] - Rev 91

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