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200 raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers jguarin2002 4492d 20h /raytrac/branches/
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4509d 02h /raytrac/branches/
198 Check out for the best out for the best organization so the datapath does not consume to many logic cells jguarin2002 4509d 02h /raytrac/branches/
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4519d 03h /raytrac/branches/
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4522d 14h /raytrac/branches/
195 Document advance and changes in the design jguarin2002 4525d 11h /raytrac/branches/
194 Work In Progress jguarin2002 4540d 17h /raytrac/branches/
193 WIP: Main Document jguarin2002 4541d 14h /raytrac/branches/
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4542d 02h /raytrac/branches/
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4542d 02h /raytrac/branches/
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4546d 10h /raytrac/branches/
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4546d 16h /raytrac/branches/
188 Fitting Report jguarin2002 4547d 23h /raytrac/branches/
187 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4548d 00h /raytrac/branches/
186 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4548d 00h /raytrac/branches/
185 Well mulblock was a void inside file.... jguarin2002 4548d 13h /raytrac/branches/
184 Se quitó la palabra capítulo de los titulos de los capítulos. jguarin2002 4548d 17h /raytrac/branches/
183 Se quitó la palabra capítulo de los titulos de los capítulos. jguarin2002 4548d 17h /raytrac/branches/
182 Sobre la sincronización del RayTrac al escribir instrucciones y operandos. Pagina 29 y 31. jguarin2002 4548d 18h /raytrac/branches/
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4549d 01h /raytrac/branches/

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