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Rev Log message Author Age Path
255 Documento Final con primeros resultados de desempeño jguarin2002 4275d 04h /raytrac/branches/
254 ... jguarin2002 4277d 23h /raytrac/branches/
253 .... jguarin2002 4277d 23h /raytrac/branches/
252 Performance Results on the Raytrac jguarin2002 4279d 03h /raytrac/branches/
251 Es claro.... jguarin2002 4279d 03h /raytrac/branches/
250 Design changed..... doubts about OS using jguarin2002 4279d 03h /raytrac/branches/
249 Using a register as a 66.5 MHZ timer counter jguarin2002 4281d 17h /raytrac/branches/
248 Corrected an error on the normal jguarin2002 4289d 23h /raytrac/branches/
247 Advance in application... but some normalization problems had popped up jguarin2002 4290d 15h /raytrac/branches/
246 framework for conditional and accumulative operations DESCRIBED NOT IMPLEMENTED jguarin2002 4297d 03h /raytrac/branches/
245 Avances pequenos en los documentos jguarin2002 4309d 22h /raytrac/branches/
244 Changed the directory structure a little bit, there is now wide arith (which encapsulates in a single RTL 3 adders or 3 adders jguarin2002 4312d 20h /raytrac/branches/
243 The Registers BASE+1, BASE+2, BASE+3 are used now for debugging purposes jguarin2002 4312d 20h /raytrac/branches/
242 AS1 produced an unnoticed delay, the compiler geenerated an extra stage..... so a delay constant was added to sync this extra stage with the operation via ssync_chain jguarin2002 4312d 20h /raytrac/branches/
241 fmul32 x 6 multipliers wide jguarin2002 4313d 17h /raytrac/branches/
240 last minute correction jguarin2002 4313d 21h /raytrac/branches/
239 wide multiplicator added to avoid optimization jguarin2002 4313d 21h /raytrac/branches/
238 wide multiplicator added to avoid optimization jguarin2002 4313d 21h /raytrac/branches/
237 corrected errors in raytrac.vhd jguarin2002 4313d 23h /raytrac/branches/
236 Tunnning delay added to q0 queue jguarin2002 4314d 02h /raytrac/branches/

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