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[/] [raytrac/] [branches/] [fp/] - Rev 166

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Rev Log message Author Age Path
166 A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way jguarin2002 4463d 09h /raytrac/branches/fp/
165 Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor) jguarin2002 4463d 18h /raytrac/branches/fp/
164 reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again jguarin2002 4464d 19h /raytrac/branches/fp/
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4464d 21h /raytrac/branches/fp/
162 Señales para evaluar en simulación funcional jguarin2002 4464d 21h /raytrac/branches/fp/
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4466d 12h /raytrac/branches/fp/
160 Corrections derived from simulation debugging jguarin2002 4471d 05h /raytrac/branches/fp/
159 wrcycle\!\? No\! rwcycle.... jguarin2002 4472d 15h /raytrac/branches/fp/
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4472d 19h /raytrac/branches/fp/
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4473d 07h /raytrac/branches/fp/
156 Test Bench Beta 0.1 jguarin2002 4473d 19h /raytrac/branches/fp/
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4476d 19h /raytrac/branches/fp/
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4479d 11h /raytrac/branches/fp/
153 last modifications for tb_compiler.py compliance jguarin2002 4479d 11h /raytrac/branches/fp/
152 Test bench oriented modifications jguarin2002 4483d 12h /raytrac/branches/fp/
151 Previous Work to generate test benching jguarin2002 4542d 08h /raytrac/branches/fp/
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4556d 05h /raytrac/branches/fp/
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4556d 08h /raytrac/branches/fp/
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4556d 09h /raytrac/branches/fp/
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4558d 21h /raytrac/branches/fp/

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