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[/] [raytrac/] [branches/] [fp/] - Rev 167

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Rev Log message Author Age Path
167 Corrections on the moment the dot product and normalization queues are "rd_ack\'ed", they were a cycle earlier than they should causing pipeline desync jguarin2002 4484d 16h /raytrac/branches/fp/
166 A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way jguarin2002 4485d 03h /raytrac/branches/fp/
165 Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor) jguarin2002 4485d 11h /raytrac/branches/fp/
164 reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again jguarin2002 4486d 13h /raytrac/branches/fp/
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4486d 15h /raytrac/branches/fp/
162 Señales para evaluar en simulación funcional jguarin2002 4486d 15h /raytrac/branches/fp/
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4488d 06h /raytrac/branches/fp/
160 Corrections derived from simulation debugging jguarin2002 4492d 22h /raytrac/branches/fp/
159 wrcycle\!\? No\! rwcycle.... jguarin2002 4494d 08h /raytrac/branches/fp/
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4494d 12h /raytrac/branches/fp/
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4495d 00h /raytrac/branches/fp/
156 Test Bench Beta 0.1 jguarin2002 4495d 12h /raytrac/branches/fp/
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4498d 13h /raytrac/branches/fp/
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4501d 04h /raytrac/branches/fp/
153 last modifications for tb_compiler.py compliance jguarin2002 4501d 04h /raytrac/branches/fp/
152 Test bench oriented modifications jguarin2002 4505d 06h /raytrac/branches/fp/
151 Previous Work to generate test benching jguarin2002 4564d 02h /raytrac/branches/fp/
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4577d 23h /raytrac/branches/fp/
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4578d 02h /raytrac/branches/fp/
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4578d 02h /raytrac/branches/fp/

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