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Rev Log message Author Age Path
210 Document advance..... towards dma oriented raytrac jguarin2002 4362d 17h /raytrac/branches/fp/
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4378d 23h /raytrac/branches/fp/
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4389d 00h /raytrac/branches/fp/
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4392d 12h /raytrac/branches/fp/
195 Document advance and changes in the design jguarin2002 4395d 08h /raytrac/branches/fp/
194 Work In Progress jguarin2002 4410d 14h /raytrac/branches/fp/
193 WIP: Main Document jguarin2002 4411d 11h /raytrac/branches/fp/
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4411d 23h /raytrac/branches/fp/
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4411d 23h /raytrac/branches/fp/
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4416d 07h /raytrac/branches/fp/
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4416d 14h /raytrac/branches/fp/
188 Fitting Report jguarin2002 4417d 21h /raytrac/branches/fp/
187 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4417d 21h /raytrac/branches/fp/
186 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4417d 21h /raytrac/branches/fp/
185 Well mulblock was a void inside file.... jguarin2002 4418d 10h /raytrac/branches/fp/
184 Se quitó la palabra capítulo de los titulos de los capítulos. jguarin2002 4418d 14h /raytrac/branches/fp/
183 Se quitó la palabra capítulo de los titulos de los capítulos. jguarin2002 4418d 14h /raytrac/branches/fp/
182 Sobre la sincronización del RayTrac al escribir instrucciones y operandos. Pagina 29 y 31. jguarin2002 4418d 15h /raytrac/branches/fp/
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4418d 22h /raytrac/branches/fp/
180 Documentos de diseño y documento final jguarin2002 4418d 22h /raytrac/branches/fp/

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