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[/] [raytrac/] [branches/] [fp/] - Rev 242

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Rev Log message Author Age Path
231 nfetch address counter implemented in a whole register for convinience jguarin2002 4314d 11h /raytrac/branches/fp/
227 Fixed a BUG where big differences betweeen exponents difference suffered from miss-signedness because of the width of the result was 1 bit narrower, and still its highest significant bit was taken as the sign, in result big differences in where taken as negative results... leading to situations like A+0=0 cause the exponent chosen as the big one was the zero's (-127) leading to an unexpected 0 in the result. The bug was fixed by correcting the signedness of the operation and making the result less narrower in one bit. jguarin2002 4322d 10h /raytrac/branches/fp/
226 Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia jguarin2002 4322d 11h /raytrac/branches/fp/
225 Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia jguarin2002 4322d 12h /raytrac/branches/fp/
224 Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia jguarin2002 4322d 12h /raytrac/branches/fp/
223 Reportes para NS_JULI_SDF_ASM_AP_DMA_130812_21028 jguarin2002 4329d 11h /raytrac/branches/fp/
222 documento en un 55\% jguarin2002 4329d 11h /raytrac/branches/fp/
210 Document advance..... towards dma oriented raytrac jguarin2002 4344d 07h /raytrac/branches/fp/
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4360d 14h /raytrac/branches/fp/
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4370d 15h /raytrac/branches/fp/
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4374d 02h /raytrac/branches/fp/
195 Document advance and changes in the design jguarin2002 4376d 23h /raytrac/branches/fp/
194 Work In Progress jguarin2002 4392d 05h /raytrac/branches/fp/
193 WIP: Main Document jguarin2002 4393d 02h /raytrac/branches/fp/
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4393d 13h /raytrac/branches/fp/
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4393d 13h /raytrac/branches/fp/
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4397d 22h /raytrac/branches/fp/
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4398d 04h /raytrac/branches/fp/
188 Fitting Report jguarin2002 4399d 11h /raytrac/branches/fp/
187 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4399d 11h /raytrac/branches/fp/

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