URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

[/] [rio/] - Rev 20

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Rev	Log message	Author	Age	Path
20	Adding software C-stack and matching VHDL modules.	magro732	3966d 23h	/rio/
19	Removing synthesis warnings.	magro732	3991d 23h	/rio/
18	Making RioSerial entity the same as before+minor fixes.	magro732	3992d 21h	/rio/
17	Removing latch and improving timing.	magro732	3993d 22h	/rio/
16	Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing.	magro732	3993d 22h	/rio/
15	All testcases are ok. Still needs some tweeks though.	magro732	3997d 23h	/rio/
14	Most issues solved, testbench issues remains.	magro732	4000d 22h	/rio/
13	Timeouts are working.	magro732	4003d 23h	/rio/
12	Backup of recent work, debugging new RioSerial.	magro732	4014d 22h	/rio/
11	Receiver ready, transmitter is compiling.	magro732	4014d 22h	/rio/
10	Branch to develop support for parallel symbols.	magro732	4014d 23h	/rio/
9	Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)	azdem	4056d 10h	/rio/
8	Adding signal descriptions in comments.	magro732	4100d 00h	/rio/
7	Adding missing generic parameters to RioPacketBuffer.	magro732	4187d 03h	/rio/
6	Adding RioWbBridge. Sorry, no testbench for this one.	magro732	4187d 05h	/rio/
5	Uploading primitive documentation.	magro732	4193d 22h	/rio/
4	Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification.	magro732	4216d 11h	/rio/
3	Adding RioPacketBuffer and testbench.	magro732	4217d 03h	/rio/
2	Adding RioSwitch and testbench.	magro732	4217d 05h	/rio/
1	The project and the structure was created	root	4218d 11h	/rio/

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Subversion Repositories rio

[/] [rio/] - Rev 20

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