URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

[/] [rio/] - Rev 23

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Rev	Log message	Author	Age	Path
23	Tagging alpha release 2.0.0.	magro732	3879d 00h	/rio/
22	Tagging release 1.0.0.	magro732	3879d 00h	/rio/
21	Branching of a single symbol version of the new RioSerial.	magro732	3879d 00h	/rio/
20	Adding software C-stack and matching VHDL modules.	magro732	3944d 02h	/rio/
19	Removing synthesis warnings.	magro732	3969d 02h	/rio/
18	Making RioSerial entity the same as before+minor fixes.	magro732	3970d 01h	/rio/
17	Removing latch and improving timing.	magro732	3971d 01h	/rio/
16	Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing.	magro732	3971d 02h	/rio/
15	All testcases are ok. Still needs some tweeks though.	magro732	3975d 03h	/rio/
14	Most issues solved, testbench issues remains.	magro732	3978d 02h	/rio/
13	Timeouts are working.	magro732	3981d 02h	/rio/
12	Backup of recent work, debugging new RioSerial.	magro732	3992d 01h	/rio/
11	Receiver ready, transmitter is compiling.	magro732	3992d 02h	/rio/
10	Branch to develop support for parallel symbols.	magro732	3992d 02h	/rio/
9	Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)	azdem	4033d 14h	/rio/
8	Adding signal descriptions in comments.	magro732	4077d 03h	/rio/
7	Adding missing generic parameters to RioPacketBuffer.	magro732	4164d 07h	/rio/
6	Adding RioWbBridge. Sorry, no testbench for this one.	magro732	4164d 09h	/rio/
5	Uploading primitive documentation.	magro732	4171d 01h	/rio/
4	Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification.	magro732	4193d 14h	/rio/

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[/] [rio/] - Rev 23

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