URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

[/] [rio/] - Rev 28

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Rev	Log message	Author	Age	Path
28	Correcting bug in RioSwitch.vhd internal Wishbone interconnect. Modifying an existing test case in TestRioSwitch.vhd to provoke the error.	magro732	3665d 07h	/rio/
27	Adding missing code to single-symbol pipelined transmitter. Not tested nor copiled.	magro732	3666d 18h	/rio/
26	Temporary checkin of parallelSymbols branch. It does not work yet.	magro732	3827d 06h	/rio/
25	Correcting compiler errors in TestRioPcsUart.vhd	magro732	3833d 23h	/rio/
24	Changing errornous use statement.	magro732	3834d 00h	/rio/
23	Tagging alpha release 2.0.0.	magro732	3950d 17h	/rio/
22	Tagging release 1.0.0.	magro732	3950d 18h	/rio/
21	Branching of a single symbol version of the new RioSerial.	magro732	3950d 18h	/rio/
20	Adding software C-stack and matching VHDL modules.	magro732	4015d 20h	/rio/
19	Removing synthesis warnings.	magro732	4040d 19h	/rio/
18	Making RioSerial entity the same as before+minor fixes.	magro732	4041d 18h	/rio/
17	Removing latch and improving timing.	magro732	4042d 19h	/rio/
16	Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing.	magro732	4042d 19h	/rio/
15	All testcases are ok. Still needs some tweeks though.	magro732	4046d 20h	/rio/
14	Most issues solved, testbench issues remains.	magro732	4049d 19h	/rio/
13	Timeouts are working.	magro732	4052d 20h	/rio/
12	Backup of recent work, debugging new RioSerial.	magro732	4063d 19h	/rio/
11	Receiver ready, transmitter is compiling.	magro732	4063d 19h	/rio/
10	Branch to develop support for parallel symbols.	magro732	4063d 19h	/rio/
9	Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)	azdem	4105d 07h	/rio/

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Subversion Repositories rio

[/] [rio/] - Rev 28

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