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URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

[/] [rio/] [tags/] [1.0.2-release/] - Rev 50

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Rev	Log message	Author	Age	Path
50	Tagging 1.0.2 including new SW-stack where the packet API has been detached.	magro732	3473d 02h	/rio/tags/1.0.2-release/
49	Moving packet generation API from riostack.c to new file riopacket.c. The riostack.c is now transparent to all packets and does not answer on its own to maintenance packets. That now has to be handled in the user-written code that instantiates the riostack. Moving all regression tests into new files test_riostack.c and test_riopacket.c.	magro732	3473d 02h	/rio/trunk/
28	Correcting bug in RioSwitch.vhd internal Wishbone interconnect. Modifying an existing test case in TestRioSwitch.vhd to provoke the error.	magro732	3606d 06h	/rio/trunk/
25	Correcting compiler errors in TestRioPcsUart.vhd	magro732	3774d 23h	/rio/trunk/
24	Changing errornous use statement.	magro732	3774d 23h	/rio/trunk/
20	Adding software C-stack and matching VHDL modules.	magro732	3956d 19h	/rio/trunk/
9	Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)	azdem	4046d 06h	/rio/trunk/
8	Adding signal descriptions in comments.	magro732	4089d 19h	/rio/trunk/
7	Adding missing generic parameters to RioPacketBuffer.	magro732	4176d 23h	/rio/trunk/
6	Adding RioWbBridge. Sorry, no testbench for this one.	magro732	4177d 01h	/rio/trunk/
5	Uploading primitive documentation.	magro732	4183d 17h	/rio/trunk/
4	Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification.	magro732	4206d 07h	/rio/trunk/
3	Adding RioPacketBuffer and testbench.	magro732	4206d 23h	/rio/trunk/
2	Adding RioSwitch and testbench.	magro732	4207d 00h	/rio/trunk/
1	The project and the structure was created	root	4208d 07h	/rio/trunk/

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