URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

[/] [rio/] [trunk/] [rtl/] [vhdl/] - Rev 42

Rev	Log message	Author	Age	Path
28	Correcting bug in RioSwitch.vhd internal Wishbone interconnect. Modifying an existing test case in TestRioSwitch.vhd to provoke the error.	magro732	3594d 22h	/rio/trunk/rtl/vhdl/
25	Correcting compiler errors in TestRioPcsUart.vhd	magro732	3763d 15h	/rio/trunk/rtl/vhdl/
20	Adding software C-stack and matching VHDL modules.	magro732	3945d 11h	/rio/trunk/rtl/vhdl/
9	Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)	azdem	4034d 22h	/rio/trunk/rtl/vhdl/
8	Adding signal descriptions in comments.	magro732	4078d 12h	/rio/trunk/rtl/vhdl/
7	Adding missing generic parameters to RioPacketBuffer.	magro732	4165d 15h	/rio/trunk/rtl/vhdl/
6	Adding RioWbBridge. Sorry, no testbench for this one.	magro732	4165d 18h	/rio/trunk/rtl/vhdl/
4	Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification.	magro732	4194d 23h	/rio/trunk/rtl/vhdl/
3	Adding RioPacketBuffer and testbench.	magro732	4195d 15h	/rio/trunk/rtl/vhdl/
2	Adding RioSwitch and testbench.	magro732	4195d 17h	/rio/trunk/rtl/vhdl/