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Rev Log message Author Age Path
37 Applied VHDL indent. jlechner 6413d 18h /rise/trunk/
36 - Testbench for RISE. cwalter 6413d 18h /rise/trunk/
35 - Testbench for register file. cwalter 6413d 18h /rise/trunk/
34 - Filex have been renamed to have tb prefix. cwalter 6413d 18h /rise/trunk/
33 - Fixed process sensitivity list. cwalter 6413d 19h /rise/trunk/
32 - When this stage asserts stall_out it must clear the input for the next
stage.
- Fixed process sensitivity list.		 cwalter 6413d 19h /rise/trunk/
31 - Added PC_RESET_VECTOR constant. cwalter 6413d 21h /rise/trunk/
30 - Top level testbench for RISE. cwalter 6413d 21h /rise/trunk/
29 - Initial version of IF stage with dummy instructions. cwalter 6413d 21h /rise/trunk/
28 Added new register write enable signals. jlechner 6415d 14h /rise/trunk/
27 Added new register write enable signals to component instantiation of register_file and wb_stage. jlechner 6415d 14h /rise/trunk/
26 Applied VHDL indent. jlechner 6415d 14h /rise/trunk/
25 netlist file for the memories
is needed for IMEM and DMEM		 ustadler 6416d 14h /rise/trunk/
24 4k Data Instruction for Spartan 3 (Block RAM)
Added write enable to the entity		 ustadler 6416d 14h /rise/trunk/
23 4k Data Memory for Spartan 3 (Block RAM)
Added write enable to the entity		 ustadler 6416d 14h /rise/trunk/
22 testbench für die register file ustadler 6417d 04h /rise/trunk/
21 überarbeitet. asynchrones lesen und synchrones schreiben. dreg_enable, sr_enable und lr_enable zur entity hinzugefügt ustadler 6417d 15h /rise/trunk/
20 - Fixed bug where SR fetch code locked wrong register. cwalter 6417d 17h /rise/trunk/
19 Version 1.2 der register file ustadler 6418d 01h /rise/trunk/
18 Update of pipeline schematics:
- Fixed errors
- Changed names of some signals so they are equal with VHDL code
- Added second register lock port		 jlechner 6418d 20h /rise/trunk/

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