OpenCores
URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] - Rev 110

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
110 - Added missing file to CVS. cwalter 6420d 14h /rise/trunk/vhdl/
107 - Added new example for memory testing. cwalter 6421d 06h /rise/trunk/vhdl/
106 - ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT. cwalter 6421d 06h /rise/trunk/vhdl/
105 - OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT. cwalter 6421d 06h /rise/trunk/vhdl/
104 - Added missing signal dmem_data_in. cwalter 6421d 07h /rise/trunk/vhdl/
102 changed data pitch ustadler 6423d 12h /rise/trunk/vhdl/
101 - Signals for memory block where not always set. This resulted in a latch. cwalter 6423d 12h /rise/trunk/vhdl/
100 - Signal clear_in was missing in sensitivity list. cwalter 6423d 12h /rise/trunk/vhdl/
99 - Fixed problem with barrel shifter input signals where a latch has been
synthesized.
cwalter 6423d 12h /rise/trunk/vhdl/
98 - Applied indenting tool. cwalter 6423d 12h /rise/trunk/vhdl/
97 Fixed bug: only set branch and clear signals if branch is actually executed. jlechner 6423d 13h /rise/trunk/vhdl/
96 - SR register is now computed in ALU stage. cwalter 6423d 14h /rise/trunk/vhdl/
95 - Write back now only updates SR in case of a LOAD. cwalter 6423d 14h /rise/trunk/vhdl/
94 Added signal from ex stage to register lock unit for clearing all register locks
when a branch is executed.
jlechner 6423d 14h /rise/trunk/vhdl/
93 Changed behavior on branch. Current PC is immeadiately taken from ex stage alu result. jlechner 6423d 14h /rise/trunk/vhdl/
92 Added logic for inserting a nop instruction when the pipeline is cleared. jlechner 6423d 14h /rise/trunk/vhdl/
91 - Computed new SR values from ALU result. cwalter 6423d 14h /rise/trunk/vhdl/
90 Added output signal for clearing all register locks when a branch instruction is executed.
This is necessary because the id stage could have locked registers for an instruction
that is cleared out of the pipeline due to the branch.
jlechner 6423d 14h /rise/trunk/vhdl/
89 Added input signal for clearing all register locks. jlechner 6423d 14h /rise/trunk/vhdl/
86 - Added new example for a more complex loop. cwalter 6423d 15h /rise/trunk/vhdl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.