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[/] [rise/] [trunk/] [vhdl/] - Rev 117

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Rev	Log message	Author	Age	Path
117	Uart im mem_stage	trinklhar	6414d 04h	/rise/trunk/vhdl/
116	writes to uart when write to reg 0	trinklhar	6415d 11h	/rise/trunk/vhdl/
115	* empty log message *	trinklhar	6416d 01h	/rise/trunk/vhdl/
114	Uart 0.3	trinklhar	6417d 05h	/rise/trunk/vhdl/
113	Uart reset funkt	trinklhar	6417d 06h	/rise/trunk/vhdl/
112	Uart drin aber signale nicht eingebunden	trinklhar	6417d 07h	/rise/trunk/vhdl/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6419d 23h	/rise/trunk/vhdl/
110	- Added missing file to CVS.	cwalter	6420d 06h	/rise/trunk/vhdl/
107	- Added new example for memory testing.	cwalter	6420d 22h	/rise/trunk/vhdl/
106	- ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT.	cwalter	6420d 22h	/rise/trunk/vhdl/
105	- OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT.	cwalter	6420d 22h	/rise/trunk/vhdl/
104	- Added missing signal dmem_data_in.	cwalter	6420d 22h	/rise/trunk/vhdl/
102	changed data pitch	ustadler	6423d 03h	/rise/trunk/vhdl/
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6423d 04h	/rise/trunk/vhdl/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6423d 04h	/rise/trunk/vhdl/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6423d 04h	/rise/trunk/vhdl/
98	- Applied indenting tool.	cwalter	6423d 04h	/rise/trunk/vhdl/
97	Fixed bug: only set branch and clear signals if branch is actually executed.	jlechner	6423d 05h	/rise/trunk/vhdl/
96	- SR register is now computed in ALU stage.	cwalter	6423d 05h	/rise/trunk/vhdl/
95	- Write back now only updates SR in case of a LOAD.	cwalter	6423d 05h	/rise/trunk/vhdl/

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[/] [rise/] [trunk/] [vhdl/] - Rev 117

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