URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] - Rev 120

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
120	Added UART module to memory entity	trinklhar	6364d 20h	/rise/trunk/vhdl/
119	Uart wieder ausgebaut	trinklhar	6365d 15h	/rise/trunk/vhdl/
118	insert Uart address constant	trinklhar	6365d 15h	/rise/trunk/vhdl/
117	Uart im mem_stage	trinklhar	6365d 15h	/rise/trunk/vhdl/
116	writes to uart when write to reg 0	trinklhar	6366d 21h	/rise/trunk/vhdl/
115	* empty log message *	trinklhar	6367d 11h	/rise/trunk/vhdl/
114	Uart 0.3	trinklhar	6368d 16h	/rise/trunk/vhdl/
113	Uart reset funkt	trinklhar	6368d 17h	/rise/trunk/vhdl/
112	Uart drin aber signale nicht eingebunden	trinklhar	6368d 18h	/rise/trunk/vhdl/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6371d 10h	/rise/trunk/vhdl/
110	- Added missing file to CVS.	cwalter	6371d 17h	/rise/trunk/vhdl/
107	- Added new example for memory testing.	cwalter	6372d 09h	/rise/trunk/vhdl/
106	- ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT.	cwalter	6372d 09h	/rise/trunk/vhdl/
105	- OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT.	cwalter	6372d 09h	/rise/trunk/vhdl/
104	- Added missing signal dmem_data_in.	cwalter	6372d 09h	/rise/trunk/vhdl/
102	changed data pitch	ustadler	6374d 14h	/rise/trunk/vhdl/
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6374d 15h	/rise/trunk/vhdl/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6374d 15h	/rise/trunk/vhdl/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6374d 15h	/rise/trunk/vhdl/
98	- Applied indenting tool.	cwalter	6374d 15h	/rise/trunk/vhdl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] - Rev 120

Filtering Options