URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] - Rev 127

Rev	Log message	Author	Age	Path
127	Changed high active resets to low active ones.	jlechner	6377d 22h	/rise/trunk/vhdl/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6378d 04h	/rise/trunk/vhdl/
125	Fixed vhdl bugs	trinklhar	6378d 04h	/rise/trunk/vhdl/
124	Assigned UART signals to ports on top-level entity	trinklhar	6378d 04h	/rise/trunk/vhdl/
123	Removed UART again	trinklhar	6378d 05h	/rise/trunk/vhdl/
122	Removed UART again again	trinklhar	6378d 05h	/rise/trunk/vhdl/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6378d 05h	/rise/trunk/vhdl/
120	Added UART module to memory entity	trinklhar	6378d 05h	/rise/trunk/vhdl/
119	Uart wieder ausgebaut	trinklhar	6379d 00h	/rise/trunk/vhdl/
118	insert Uart address constant	trinklhar	6379d 00h	/rise/trunk/vhdl/
117	Uart im mem_stage	trinklhar	6379d 00h	/rise/trunk/vhdl/
116	writes to uart when write to reg 0	trinklhar	6380d 07h	/rise/trunk/vhdl/
115	* empty log message *	trinklhar	6380d 21h	/rise/trunk/vhdl/
114	Uart 0.3	trinklhar	6382d 01h	/rise/trunk/vhdl/
113	Uart reset funkt	trinklhar	6382d 02h	/rise/trunk/vhdl/
112	Uart drin aber signale nicht eingebunden	trinklhar	6382d 03h	/rise/trunk/vhdl/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6384d 19h	/rise/trunk/vhdl/
110	- Added missing file to CVS.	cwalter	6385d 02h	/rise/trunk/vhdl/
107	- Added new example for memory testing.	cwalter	6385d 18h	/rise/trunk/vhdl/
106	- ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT.	cwalter	6385d 18h	/rise/trunk/vhdl/